Dynamic random access memory (DRAM) devices are the most common type of semiconductor memory used for data storage and, thus, are found in many integrated circuit designs. A generic DRAM device includes a plurality of substantially identical semiconductor memory cell arrays, a plurality of bit lines, and a plurality of word lines that intersect the bit lines. Each memory cell array consists of multiple memory cells arranged in a matrix of addressable rows and columns. One of the word lines and one of the bit lines intersects the location of each individual memory cell in the memory cell array.
Each individual memory cell includes a storage capacitor for storing data and an access transistor, such as a planar or vertical metal oxide semiconductor field-effect transistor (MOSFET) or a fin-type field effect transistor (FinFET), serially connected with the storage transistor. During read and write operations, the access transistor controls the transfer of data charges to and from the storage capacitor. Because DRAM devices are a type of volatile memory that leaks stored charge, the data charge on the storage capacitor of each memory cell is periodically refreshed during a refresh operation. Either the source or drain of the access transistor is electrically connected to a corresponding bit line and the gate of the access device is electrically connected to a corresponding word line. In certain DRAM device designs, memory cells are arranged in pairs to allow sharing of a bit line contact, which significantly reduces the overall memory cell size.
When a signal routed on a word line activates the access transistor of one of the memory cells, the storage capacitor of the activated memory cell transfers a data signal to the bit line connected to the memory cell or a data signal from the bit line to the storage capacitor of the memory cell. When data stored in one of the memory cells is read onto one of the bit lines, a potential difference is generated between the bit line of the respective memory cell and the bit line of another memory cell, which form a bit line pair. A bit line sense amplifier connected to the data line pair senses and amplifies the potential difference and transfers the data from the selected memory cells to a data line pair.
The storage capacitor includes a capacitor node formed by filling a deep trench with a conductor and a buried plate defined in the substrate about the deep trench. The buried plate is electrically isolated from the capacitor node by a thin node dielectric formed on the trench sidewalls. An isolation collar is required to isolate the storage capacitor electrically from the access transistor. Specifically, the isolation collar suppresses leakage and loss of charge stored by the storage capacitor arising from a vertical parasitic transistor induced in the semiconductor body in which the deep trench storage capacitor is formed. Specifically, the parasitic transistor is established between the source/drain region of the access transistor coupled with the capacitor node and the buried capacitor plate, which respectively operate as a source and drain of the parasitic transistor. The capacitor node operates as a gate of the parasitic transistor.
Traditionally, the isolation collar has consisted of an insulating material, such as oxide, formed on the trench sidewalls. However, these conventional isolation collars undesirably narrow the trench opening by projecting into the trench and, thus, increase the series resistance of the storage capacitor. Increasing the series resistance with the storage capacitor impedes charge transfer and retards read and write operations. Although the storage capacitor and access transistor may be scaled to smaller dimensions, the isolation collar is non-scalable because a minimum thickness of insulating material is required to suppress leakage of stored charge. Consequently, shrinking the trench dimensions to reduce the feature size of the storage capacitor and, optionally, the access transistor causes the trench resistance to rise to potentially unacceptable levels. Moreover, as the trench dimensions shrink, the trench becomes increasingly difficult to fill with a conductor to form the capacitor node. Specifically, the dimensions of the isolation collar must remain constant as the trench dimensions shrink. Hence, the trench constriction presented by the projecting isolation collar becomes more pronounced and significant with shrinking trench dimensions. The occluded trench may precipitate a yield loss for the process of forming the storage capacitors, which may be expected to increase with decreasing trench dimensions.
One conventional approach for solving this dilemma is to form a partially buried isolation collar outside of the deep trench by a local oxidation of silicon (LOCOS) process. However, the LOCOS process oxidizes the trench sidewalls to form the isolation collar. The LOCOS isolation collar comprises a first portion that is buried in the trench sidewall, and a second portion that protrudes into the trench. The second portion of the LOCOS collar, which protrudes into the trench, may be greater than half of the total thickness of the LOCOS isolation collar. As such, the LOCOS collar also hinders scalability of the DRAM storage trench dimensions. Because the trench sidewalls comprise various crystallographic orientations and oxidation rate exhibits a crystallographic orientation dependence, the oxide collar is not uniform around its perimeter. The LOCOS process is also complex and expensive because the deep trench must be filled with sacrificial polysilicon that is recessed multiple times and multiple dielectric layers must be deposited on the trench sidewalls as the sacrificial polysilicon is recessed. Moreover, the sacrificial polysilicon is removed from the deep trench after forming the partially buried isolation collar which, among other deleterious effects, generates defects and damages alignment marks.
What is needed, therefore, is a method for forming a buried isolation collar for a memory cell having a deep trench storage capacitor that overcomes the disadvantages of conventional methods of manufacturing such semiconductor structures.